Signal Integrity Analysis with Third-Party Tools

As FPGA devices are used in high-speed applications, signal integrity and timingmargin between the FPGA and other devices on the printed circuit board (PCB) are important aspects to consider to ensure proper systemoperation. To avoid time-consuming redesigns and expensive board respins, the topology and routing of critical signals must be simulated. The high-speed interfaces available on current FPGA devices must be modeled accurately and integrated into timing models and board-level signal integrity simulations. The tools used in the design of an FPGA and its integration into a PCBmust be “board-aware”—able to take into account properties of the board routing and the connected devices on the board. The Quartus II software provides methodologies, resources, and tools to ensure good signal integrity and timing margin between Altera FPGA devices and other components on the board. Three types of analysis are possible with the Quartus II software: